Having several years of experience in SoC Physical Design and synthesis. Key responsibilities include Synthesis, Floorplanning, Placement, Power planning, Clock Tree Synthesis and Routing, ECO and Sign off. Having good hold over Tool Command Language. Also, having good knowledge in timing closure along with STA. Experience in working on projects from sub-micron technology nodes TSMC-3nm, Samsung 7nm. Etc.
Looking forward to moving US, to uuscale my interpersonal skills. Want to learn more and upgrade skills in the new Job environment.
Fusion Compiler