Summary
Overview
Work History
Education
Skills
Languages
Timeline
Generic

Padmanjani Satti

Bangalore

Summary

Accomplished RTL Design Engineer with two and a half years of experience in ASIC design, specializing in RTL coding, logic synthesis and verification. Demonstrates proficiency in Verilog, and skilled in high-performance digital circuit design and tool-flow activities. Adept at utilizing EDA tools, with strong analytical capabilities that foster team success.

Overview

3
3
years of professional experience

Work History

ASIC Digital Design Engineer

Synopsys
Bangalore
06.2023 - Current
  • Owned RTL specification of I3C IP for both commercial and functional safety, automotive applications.
  • Developed RTL for automotive application functional safety features for controller, secondary controller and target configurations of the IP.
  • Supported over 30 customer issues at various stages of design cycle, and contributed to 15+ timely releases to customers.

Education

Bachelor of Technology - Electronics And Communication Engineering

National Institute of Technology
Tiruchirappalli
06-2023

Skills

  • RTL design and coding
  • RTL quality checks for lint, CDC and RDC
  • RTL design for functional safety in automotive applications
  • Bus protocols: AMBA (AXI, AHB, APB)
  • EDA tools: Spyglass, Vcspyglass, Design Compiler, Fusion Compiler, Formality, PrimeTime, Verdi
  • Scripting (Python, Tcl)
  • Software languages (C language)
  • Technical documentation

Languages

English
Proficient (C2)
C2
Telugu
Native
Native
Hindi
Elementary (A2)
A2

Timeline

ASIC Digital Design Engineer

Synopsys
06.2023 - Current

Bachelor of Technology - Electronics And Communication Engineering

National Institute of Technology
Padmanjani Satti