PARVATHY R

• Design of full custom sram IPs for mid level cache for intel’s latest generation processors(P-core) on latest technology nodes
• Taken the ownership of various sram IPs , worked on PPA optimization
• Transistor level circuit design, spice verification, schematic entry and coordination with layout team
• Involved in vmin flow setup, vmin ,race margin fixes , EM/IR ,noise checks ,power and leakage simulations, timing convergence and quality fixes and brought the IPs ready for tape-in
• Post silicon data analysis
• Read assist and write assist design tuning
• Worked on various design optimization activities in sram cells like decoder,sbw block etc as part of sram library development
• Worked as noise expert of mid level cache and power management clusters
• Good understanding of transistor level memory circuit design concepts ,memory marginality, noise issues, vmin checks ,bitcell analysis
• Ability to understand architectural specifications and develop custom circuits which meet stringent performance, area and power requirements.
• Tools used : seqver, internal tools
• Technolgy:14nm,7nm, intel20A, intel18A

SMIC28HKCP Single port and Dual port SRAM Compilers, TSMC22ULP Single Ended RegisterFile Compiler,GF55LPX Single Port SRAM Compiler

Role : DE Location : ARM

Technology : SMIC28HKCP ,TSMC22ULP, GF55LPX

• Monte carlo simulations to analyse retention fast rampup issue ESPCV ,static and dynamic circuit checks
• Leaf cell extractions and post layout simulations
• SNM,WRM,ADM ,Sense amp offset calculations and margin analysis Characterization ,data accuracy checks and leakage correlation Data validation using tight stimuli
• Trend checks, and front end validations Flat vs stitch analysis and PPA simulations

Design of 256x2xm2 SRAM Testchip and 256x32x8 full custom SRAM memory design

Role, DE Client : Foveon

Technology : TSI180nm

• Coding vectors for all test cases
• Implemented new logic for different test cases
• Internal margin measurements & qualification across required PVTs Leakage & power measurement
• Design of decoder ,control logic modules
• Post layout simulations & margin qualifications across PVTs Automation requirements for characterization

Characterization of SERDES mixed signal blocks

Role : DE

Client : Microsemi

Technology:TSMC 16nm and TSMC 28nm

• Liberate char flow setup
• Prepared test benches and vector coding for all arcs
• Setup ,hold ,delay and pincap characterization of all digital signals
• Dotlib generation,post processing and trend checks

Design and characterization of dual port RF memory compiler

Role : DE Location:ZiaSemi Technology : TSMC40nm

• Load estimation and device sizing Optimization of design based on fanout
• Margin measurements & qualification across required PVTs Coding timing definitions
• Leakage & power measurements
• Characterization,data Validation using tight stimuli and trend checks

Conversion of Single Port SRAM Compiler to Pseudo SRAM compiler

Role : DE Location:ZiaSemi Technology : TSMC40nm

• Design and implementation of new logic block
• Margin measurements & qualification across required PVTs
• Coding timing definitions ,leakage & power measurements Data Validation using tight stimuli and trend checks