Swetha S

· IP-Level Verification & Debugging: Extensive hands-on experience in verifying complex IPs, writing detailed test plans, developing UVM-based testbenches, debugging RTL/simulation issues, and driving functional coverage closure for 5 major projects

· SystemVerilog & UVM Proficiency: Expert in building scalable and reusable verification environments using SystemVerilog and UVM, with a strong focus on modular TB architecture, stimulus generation, and checker development.

· Power Management Verification: Developed verification flows for power management features such as clock/power gating, save-restore logic, and low-power mode transitions. Collaborated closely with RTL and architecture teams for validation.

· Register Verification via APB Interface: Designed and verified UVM-based testbenches for register read/write, default value checks, and backdoor/frontdoor access using APB interface, including fuse.

· Analog/Mixed-Signal Interface Experience:

· Accumulator & FLL – Based Frequency Calibration Verification : Verified accumulator-based frequency calibration and Frequency Lock Loop (FLL) logic for stable clock generation, ensuring accurate lock acquisition and tracking across varying conditions including voltage, and temperature variations.

o PLL Verification: Involved in lock detection, frequency calibration and power-up sequencing for PLL blocks integrated in SerDes

o Clock Generation with LDOs:Verified internal clock generation via LDOs, collaborating with Analog teams to ensure proper integration and functionality.

o DCO Calibration : Involved in DCO (Digitally Controlled Oscillator) calibration, utilizing both coarse and fine tuning techniques to ensure precise frequency generation across varying PVT conditions.

· RCOMP Calibration: Validated impedance calibration logic for high-speed I/Os.

· Functional Coverage & Checkers:Implemented SystemVerilog covergroups and protocol-specific checkers to monitor all operation scenarios including reset, power cycles, save/restore, and error cases. Drove coverage closure and early bug detection.

· Testcase Development: Created directed and constrained-random tests based on spec and evolving requirements. Focused on feature completeness, edge case coverage, and protocol compliance.

· Regression Debug & Root Cause Analysis: Led analysis of failing regressions using waveform debug, simulation logs, and coverage reports to identify RTL or TB issues, enabling faster turnaround and higher stability.

· Team Collaboration & Mentorship:

· Partnered with cross-functional teams in spec reviews, design bring-up, and bug triage.

· Acted as a mentor/buddy for new interns and team members, accelerating ramp-up and knowledge sharing.

• Collaborated with team members to write and optimize unit tests, contributing to improved code coverage and quality assurance..
• Developed and implemented functional assertions to validate application behavior against expected outcomes in unit and integration tests.
• Assisted in running regression tests and diagnosing failures by reproducing issues and collaborating with developers to apply fixes.