Motivated VLSI engineer with 5 months of training in Physical Design and 5 months of hands-on internship experience in Physical Verification. Skilled in DRC, LVS, ERC checks, and familiar with Calibre flow. Strong understanding of layout concepts, design rules, and debugging physical violations. Eager to contribute to high-quality chip design and sign-off processes.
Vaddu Uday Kiran Reddy, Sayed Huzaifulla Peerzade, A.S.V.N Anjaneya Seshasai, Vijay Vallabhuni, Physical DRC Hotspots in Dense ASIC Designs and Their Resolution Strategies, International Journal of Contemporary Research and Literacy Works (IJCRL).