Vaishnavi Dhote

CDC and RDC Verification for Media Graphics IP
May 2023 - Present

• Conducted comprehensive CDC and RDC checks for Graphics IP using SpyGlass and VC Static tools, ensuring robust design verification.
• Collaborated with designers and micro-architects to resolve CDC and RDC issues, implementing RTL fixes and achieving a 95% reduction in waiver usage through proper constraint application.
• Performed key SpyGlass all CDC goal checks and utilized assertions from verify_funct to validate constraints and ensure compliance with CDCLint guidelines.

FEV for Different Blocks in SoC Design
Oct 2022 - May 2023

• Verified functional equivalence of SoC designs at the partition level using FEV, ensuring consistency between Golden and Revised designs.
• Addressed floating signals in RTL using FEV_lite and conducted FEV_sim2syn to validate logical equivalence between simulation RTL and synthesis RTL, aligning pre and post-synthesis designs.
• Delivered accurate and timely FEV results with Cadence Conformal.

FishTail Flow Checks for SDC (SoC)
Oct 2021 - May 2023

• Mapped and verified RTL constraints using Refocus and Confirm, debugging unmapped constraints and flagged violations via schematics and RTL code.
• Resolved clock-related issues, including missing definitions, propagation, crossing, and exceptions, ensuring accurate constraint application.
• Reduced noise by eliminating unnecessary constraints, correcting exceptions, and defining precise clock groups to enhance design stability.

SpyGlass CDC Checks for SoC Partitions
Apr 2021 - Oct 2021

• Conducted CDC checks at the partition level for SoC using SpyGlass, ensuring design integrity.
• Utilized constraints and waivers to address and resolve CDC issues within partitions.